2005-06-23

Description:

Responsibilities: Implement quality and cost effective test methodology for highly complex IO, high pincount designs, and high performance serdes. Test methods must also be supportable on production testers and easy to automate into design's flow and tool.

Requirements: 5+ years in test - DFT test implementation, automatic test generation tool (atpg), and device testing on automatic test equipment. Familiar with ASIC design process, and have a solid understanding of logic device testing. Good communication skills are a must.

Education: Masters

Requirements:

Locations : CA - Silicon Valley/San Jose
Expertise : Engineering - Test Engineering
Education : Masters
JobType : Full-Time