A few positions open in our group:
Responsibilities
In this position, you will be part of a team developing a low-power graphics chip set. In this capacity, you will be the technical lead for the DFT effort for the entire design possessing. Your responsibilities will include but not be limited to:

- Developing and driving all DFT methodologies throughout the chip from block- level to full chip assembly
- Implementing all DFT methodologies and features including scan, BSIT, JTAG, BSCAN, burnin, and others
- Performing necessary checks to ensure quality and testability of the design including minimum fault coverage requirements, memory testing requirements, and at speed coverage
- Working closely with design team to implement all methodologies, DFT hooks and features
- Working closely with PNR team to ensure placement and timing constraints of all DFT features meet requirements

Qualifications
You must possess a Bachelor's degree with six years of experience or a Master's degree with four years of experience. Additional qualifications include:
- Experience with scan insertion, BIST insertion, BSCAN insertion, and others tool suites
- Experience with synthesis and static timing analysis tools
- Excellent organizational, planning, and communications skills
send your resume to: jingyuex@gmail.com with title as above.