Provide CAD support to analog/mixed signal design &
layout engineers. Acquire, develop & support CAD tools and methodologies to
enable the design and layout of a wide array of products (analog, RF,
mixed signal, multi-million gate SoC's ...) using the latest process
technologies. A thorough understanding of IC design flows and their
components is needed, including schematic entry, layout and verification,
preferably with experience in one or more of these. A sufficiently broad
background in electrical engineering and CAD is required so that the
candidate can provide CAD support for analog and mixed-signal design. The
position requires someone with the initiative required to solve
challenging problems, and with a strong desire to provide high-quality CAD
Sr. CAD Engineer:
Develop software to simulate and optimize analog,
mixed signal, and RF IC's, to enable fast, correct design of
high-performance circuits. Requires PhD in EE, with experience in numerical
algorithms to model and simulate physical systems with many unknowns, a record
of successful algorithm design and implementation, knowledge of IC
circuits and electromagnetics, and ability to clearly communicate complex
Physical Design Engineer
Performing physical design for complex low power systems.
Experience with place and route, static timing analysis, design for
manufacturability, floorplanning, clock tree synthesis, static and
dynamic IR drop analysis, design for test and physical synthesis.
Skills/Experience: Experience with wireless products and 90nm and
below process technologies a plus.
ASIC Design, SOC Implementation, Principal Engineer
Technically manage a group of ASIC designer for SOC
implementation. The position includes mentoring and leading a team of ASIC
engineers, work on refining ASIC methodologies, evaluate new EDA tools and
interface with EDA vendors. The candidate will be working in a very dynamic
environment and will be dealing with SOC tape outs and schedule
Asic Verification Engineer - Principal Engineer
Role: Responsible for designing and developing verification
environment components, and writing, executing and debugging tests
from testplans or functional specifications. Verification components
to be developed include Bus functional models/transactors/Bus
Interface Models, data/transaction and scenario generators, bus
monitors and checkers and coverage models.
Please send email to "Todd Lyon" "firstname.lastname@example.org" if you are interest.