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Ubicom - Logic Design and Verification Engineer
    From: Jon Schneickert      2006-08-29

        

    Looking for a Logic Design and Verification Engineer for full-time.

    Located: Sunnyvale, California

    Description:

    Will be a key member of the VLSI team defining, designing, and verifying a high performance Communications Processor chip.

    Responsibilities:
    Help define chip architecture.
    Design and Verification of functional modules.
    RTL coding, synthesis, and static timing.
    Create system, chip, and module level test benches.
    Write test specifications, and create directed and random tests to specification.
    Structural and physical chip implementation.
    Help define verification tools and methodology.
    Silicon bring-up and debugging.

    Requirements:

    BS degree or higher in EE, CS, or equivalent, MS preferred.
    3-7 years hands-on experience in logic design Working knowledge of Logic Simulators (Verilog-XL, VCS or VSIM)
    Ability to write HDL models, Verilog or VHDL.
    Ability to create test plans & write directed tests
    Programming in C/C++, Perl, and Assembly level language.
    Understanding of good design practices.

    Desirable Experience:

    Unix script programming.
    Strong knowledge in processor micro-architecture.

    If you are interested, please send your resumes to me

    如果你想留言,可以留在论坛里。

    Good Luck



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